2015/2016, Semester 1
School of Computing (Computer Science)
Modular Credits: 4
(CS2106 Operating Systems or CG2271 Realtime Operating Systems) and (CS3210 Parallel Computing or CS3220 Computer Architecture or CG3207 Computer Architecture).
Workload Components : A-B-C-D-E
A: no. of lecture hours per week
B: no. of tutorial hours per week
C: no. of lab hours per week
D: no. of hours for projects, assignments, fieldwork etc per week
E: no. of hours for preparatory work by a student per week
The world of parallel computer architecture has gone through a significant transformation in the recent years from high-end supercomputers used only for scientific applications to the multi-cores (multiple processing cores on a single chip) that are ubiquitous in mainstream computing systems including desktops, servers, and embedded systems. In the context of this exciting development, the aim of this module is to examine the design issues that are critical to modern parallel architectures. Topics include instruction-level parallelism through static and dynamic scheduling, shared memory, message-passing, and data parallel computer architectures, cache coherence protocols, hardware synchronization primitives, and memory consistency models.
Introduction to multi-core architectures
Cache coherence protocols
Memory consistency models
Mobile application processors
Explain the key technologies (e.g., pipeline, out-of-order execution, speculation) used in processor architecture for improving performance.
Demonstrate good understanding of data-level parallelism and its exploitation in GPU.
Apply the concept of cache coherence, synchronization, and memory consistency models in designing shared memory multi-processors.
Able to use processor simulators to perform design space exploration of micro-architecture with area-performance trade-off.
Combined 2-hour lecture and 1-hour tutorial per week
Final Exam (40%): 25 November Morning
Midterm (10%): 30 October Friday 1300-1400 COM1-0204