CG3207
COMPUTER ARCHITECTURE (2014/2015, Semester 1) 

 MODULE OUTLINE Created: 11-Feb-1999, Updated: 21-Aug-2014
 
Module Code CG3207
Module Title COMPUTER ARCHITECTURE
Semester Semester 1, 2014/2015
Modular Credits 4
Faculty Engineering
Department Electrical & Computer Engineering
Timetable Timetable/Teaching Staff
Module Facilitators
ASSOC PROF Bharadwaj Veeravalli Lecturer
DR Rajesh Panicker Lecturer
MR Shahzor Ahmad Instructor
ANASTACIA ALVAREZ Teaching Assistant
TRINH QUANG KIEN Teaching Assistant
DINESH THANGAVEL Teaching Assistant
WANG ZEXIN Teaching Assistant
MR Ng Gek Leng Others
Weblinks
http://wiki.nus.edu.sg/display/CG3207
CG3207 Lab Wiki
Excellent resource.Excellent resource.Excellent resource.Excellent resource.
http://cpudb.stanford.edu
A comprehensive database on CPUs
Good resource.Good resource.
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Learning Outcomes | Prerequisites | Schedule | Syllabus | Practical Work | Assessment | References


 LEARNING OUTCOMES Top

This course introduces concepts of computer organization, high-performance microprocessor design and performance evaluation. This course builds on two fundamental courses - EE2006/EE2020 Digital Design/Fundamentals and EE2024 Programming for Computer Interfaces / CG2007 Microprocessor Systems.

Deeper understanding of microprocessor design and performance evaluation is of paramount importance to computer engineers and electrical engineers working on computer hardware, embedded systems etc. This would help you to appreciate the various trade-offs involved, and to make informed choices while designing computer systems. It will also enable you to perform realistic performance evaluation of such systems – from the system level down to the gate level.



 PREREQUISITES Top

EE2007/CG2007 Microprocessor Systems or EE2024 Programming for Computer Interfaces.



 SCHEDULE Top


Lecture Schedule (tentative)
Topic Lecturer Weeks
Logic Design using VHDL  RCP 1 & 2
MIPS Instruction Set Architecture BV 3 & 4
ALU Design BV 5 & 6
Datapath and Controller design RCP 7 & 8
Techniques for performance enhancement, Pipelining etc. RCP 9 - 11
Memory design and Introduction to Multiprocessor Systems BV 12 & 13




 SYLLABUS Top
  • Logic design using VHDL in context of designing computer systems
  • General computer organization and operation of microprocessors
  • Design of arithmetic and logic units
  • Datapath and control unit design
  • Enhancing performance though pipelining etc.
  • Memory hierarchy in modern computer systems
  • Introduction to multiprocessor systems & related issues


 PRACTICAL WORK Top
This module involves a design exercise implementing a microprocessor on an FPGA using VHDL. There will be a set of labs to guide you through the process.

Lab Schedule (tentative)
Lab 1 (Weeks 3 & 4) : Synthesising VHDL code, FPGA Implementation, MIPS assembler.
Lab 2 (Weeks 6 & 7) : ALU design.
Lab 3 (Weeks 9-11)  : Datapath and controller design, pipelining.
Final evaluation (Week 13)

You will be allowed to take the FPGA home so that you can work anywhere, anytime as long as you have a computer with Xilinx tools installed. You are also free to use the lab during office hours as long as it does not interfere with the other modules using the lab. However, assistance will be available only during scheduled sessions.

Lab 1 is individual, the rest of the labs are to be done in groups of 3.


 ASSESSMENT Top

50% Labs/Project, 50% Final Exam.