This module involves a design exercise implementing a microprocessor on an FPGA using VHDL. There will be a set of labs to guide you through the process.
Lab Schedule (tentative)
Lab 1 (Weeks 3 & 4) : Synthesising VHDL code, FPGA Implementation, MIPS assembler.
Lab 2 (Weeks 6 & 7) : ALU design.
Lab 3 (Weeks 9-11) : Datapath and controller design, pipelining.
Final evaluation (Week 13)
You will be allowed to take the FPGA home so that you can work anywhere, anytime as long as you have a computer with Xilinx tools installed. You are also free to use the lab during office hours as long as it does not interfere with the other modules using the lab. However, assistance will be available only during scheduled sessions.
Lab 1 is individual, the rest of the labs are to be done in groups of 3.